troyguo / awesome-dv

Related projects ⓘ

Alternatives and complementary repositories for awesome-dv

• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆154Updated 6 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆363Updated 4 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆171Updated last year
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆254Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆172Updated 4 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆379Updated 4 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆233Updated 11 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆147Updated 4 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆483Updated 2 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆178Updated 7 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆111Updated 3 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆121Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆119Updated 3 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆93Updated 6 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆104Updated 6 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆33Updated 7 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆243Updated 8 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆123Updated last week
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆108Updated 2 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆89Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆129Updated 6 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆398Updated 2 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆76Updated 2 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆239Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆264Updated 6 months ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆91Updated 4 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆374Updated 4 months ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆73Updated 4 years ago
• Advanced-Microelectronics-Group / OpenC910_Modified
  commit rtl and build cosim env
  ☆35Updated 7 months ago