lowRISC / rocketLinks
☆32Updated 7 years ago
Alternatives and similar repositories for rocket
Users that are interested in rocket are comparing it to the libraries listed below
Sorting:
- OmniXtend cache coherence protocol☆82Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆49Updated 2 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆107Updated this week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- ☆25Updated 5 months ago
- ☆64Updated 6 years ago
- HW Design Collateral for Caliptra RoT IP☆102Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago