lizhirui / DreamCoreV2Links
☆22Updated 2 years ago
Alternatives and similar repositories for DreamCoreV2
Users that are interested in DreamCoreV2 are comparing it to the libraries listed below
Sorting:
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- ☆32Updated 4 months ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- gem5 FS模式实验手册☆44Updated 2 years ago
- ☆33Updated 8 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated last week
- Pick your favorite language to verify your chip.☆74Updated 3 weeks ago
- ☆68Updated 9 months ago
- data preprocessing scripts for gem5 output☆19Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- ☆89Updated 2 months ago
- ☆113Updated last week
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- ☆11Updated last year
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆19Updated 2 years ago
- Unit tests generator for RVV 1.0☆95Updated 3 weeks ago
- ☆86Updated 3 weeks ago
- ☆57Updated 6 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- ☆37Updated 7 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago