lizhirui / DreamCoreV2Links
☆22Updated 2 years ago
Alternatives and similar repositories for DreamCoreV2
Users that are interested in DreamCoreV2 are comparing it to the libraries listed below
Sorting:
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆24Updated this week
- ☆30Updated 2 months ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆56Updated 6 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆34Updated this week
- ☆67Updated 8 months ago
- ☆64Updated 3 years ago
- Pick your favorite language to verify your chip.☆70Updated last week
- RISC-V Matrix Specification☆22Updated 10 months ago
- ☆88Updated 3 weeks ago
- Documentation for XiangShan Design☆35Updated last week
- ☆106Updated this week
- gem5 FS模式实验手册☆44Updated 2 years ago
- ☆18Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆41Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆33Updated 7 months ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- Xiangshan deterministic workloads generator☆22Updated 5 months ago
- data preprocessing scripts for gem5 output☆19Updated 5 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆30Updated last week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- ☆83Updated 6 months ago
- Unit tests generator for RVV 1.0☆92Updated last month
- A Study of the SiFive Inclusive L2 Cache☆67Updated last year
- ☆29Updated 5 years ago