Alternatives and similar repositories for DreamCoreV2

Users that are interested in DreamCoreV2 are comparing it to the libraries listed below

• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated 4 months ago
• OSCPU / ysyxSoC
  ☆86Updated 3 months ago
• Jpz-sdju / trinity
  ☆24Updated last week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• pulp-platform / fpu
  ☆52Updated 6 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 2 months ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆66Updated 3 weeks ago
• OpenXiangShan / GEM5
  ☆93Updated this week
• wangeddie67 / ESYSim
  ☆38Updated last year
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆26Updated last week
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated 2 months ago
• OSCPU / yosys-sta
  ☆74Updated 3 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated 11 months ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆32Updated 6 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆28Updated 3 years ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆19Updated 4 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated 2 weeks ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 8 months ago