lizhirui / DreamCoreV2
☆22Updated last year
Alternatives and similar repositories for DreamCoreV2:
Users that are interested in DreamCoreV2 are comparing it to the libraries listed below
- ☆32Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆63Updated last month
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- data preprocessing scripts for gem5 output☆17Updated 2 months ago
- Pure digital components of a UCIe controller☆55Updated last week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- ☆36Updated 6 years ago
- Pick your favorite language to verify your chip.☆39Updated this week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆16Updated 3 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆51Updated 6 months ago
- ☆17Updated last year
- ☆63Updated 2 years ago
- ☆41Updated 6 years ago
- Unit tests generator for RVV 1.0☆78Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆29Updated 11 months ago
- An almost empty chisel project as a starting point for hardware design☆30Updated last month
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆15Updated 5 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- ☆79Updated 3 weeks ago
- 关于移植模型至gemmini的文档☆22Updated 2 years ago
- ☆57Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year