lizhirui / DreamCoreV2Links
☆22Updated 2 years ago
Alternatives and similar repositories for DreamCoreV2
Users that are interested in DreamCoreV2 are comparing it to the libraries listed below
Sorting:
- ☆32Updated 5 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated this week
- Advanced Architecture Labs with CVA6☆72Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Pick your favorite language to verify your chip.☆75Updated last week
- gem5 FS模式实验手册☆45Updated 2 years ago
- ☆122Updated this week
- ☆70Updated 11 months ago
- A Heterogeneous GPU Platform for Chipyard SoC☆41Updated this week
- ☆91Updated 3 months ago
- ☆33Updated 9 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆33Updated 2 months ago
- Documentation for XiangShan Design☆39Updated this week
- A Study of the SiFive Inclusive L2 Cache☆70Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 7 months ago
- data preprocessing scripts for gem5 output☆19Updated 7 months ago
- ☆64Updated 2 weeks ago
- ☆64Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- ☆57Updated 6 years ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- Xiangshan deterministic workloads generator☆24Updated 8 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆89Updated 2 months ago
- A docker image for One Student One Chip's debug exam☆10Updated 2 years ago
- RISC-V Matrix Specification☆24Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year