Advanced Architecture Labs with CVA6
☆79Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for labs-with-cva6
Users that are interested in labs-with-cva6 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆204Oct 14, 2024Updated last year
- ☆12Sep 18, 2024Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 11 months ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Dec 22, 2023Updated 2 years ago
- Custom 6502 Video Game Console☆13Mar 3, 2026Updated 3 weeks ago
- ☆22Nov 3, 2025Updated 4 months ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆66Aug 5, 2024Updated last year
- Simple UVM environment for experimenting with Verilator.☆38Updated this week
- Recommended coding standard of Verilog and SystemVerilog.☆36Oct 21, 2021Updated 4 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Nov 19, 2025Updated 4 months ago
- gem5 FS模式实验手册☆46Mar 8, 2023Updated 3 years ago
- ☆22Apr 16, 2023Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 6 years ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆506Updated this week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Mar 4, 2026Updated 3 weeks ago
- A C version of Branch Predictor Simulator☆17Jul 10, 2024Updated last year
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated 2 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆23May 8, 2025Updated 10 months ago
- This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board…☆14Aug 24, 2023Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- SystemVerilog Tutorial☆197Mar 7, 2026Updated 3 weeks ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆17Feb 2, 2026Updated last month
- ☆16Mar 18, 2025Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆140Oct 2, 2025Updated 5 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated last year
- gem5 相关中文笔记☆17Dec 2, 2021Updated 4 years ago
- QuardStar Tutorial is all you need !☆16Sep 11, 2024Updated last year
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated last month
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated 2 years ago