Advanced Architecture Labs with CVA6
☆82Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for labs-with-cva6
Users that are interested in labs-with-cva6 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 体系结构研讨 + ysyx高阶大纲 (WIP☆217Oct 14, 2024Updated last year
- ☆12Sep 18, 2024Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 7 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Dec 22, 2023Updated 2 years ago
- Custom 6502 Video Game Console☆14May 8, 2026Updated 2 months ago
- ☆22Nov 3, 2025Updated 8 months ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Jun 1, 2026Updated last month
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆67Aug 5, 2024Updated last year
- gem5 FS模式实验手册☆47Mar 8, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆23Apr 16, 2023Updated 3 years ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Simple UVM environment for experimenting with Verilator.☆44Jul 2, 2026Updated 2 weeks ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆24May 8, 2025Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆18Updated this week
- FSA: Fusing FlashAttention within a Single Systolic Array☆183Apr 15, 2026Updated 3 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board…☆14Aug 24, 2023Updated 2 years ago
- SystemVerilog Tutorial☆229Mar 7, 2026Updated 4 months ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- ☆16Mar 18, 2025Updated last year
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆18Apr 28, 2026Updated 2 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆55Jan 2, 2025Updated last year
- gem5 相关中文笔记☆16Dec 2, 2021Updated 4 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆37Oct 21, 2021Updated 4 years ago
- QuardStar Tutorial is all you need !☆19Sep 11, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last month
- ☆33Nov 25, 2022Updated 3 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆19Nov 11, 2025Updated 8 months ago
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 2 months ago
- Perceptron-based branch predictor written in C++☆14Dec 14, 2016Updated 9 years ago