fredrequin / verilator_xilinxLinks
Re-coded Xilinx primitives for Verilator use
☆50Updated 5 months ago
Alternatives and similar repositories for verilator_xilinx
Users that are interested in verilator_xilinx are comparing it to the libraries listed below
Sorting:
- SpinalHDL Hardware Math Library☆93Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- Test dashboard for verification features in Verilator☆28Updated this week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆102Updated 3 years ago
- Platform Level Interrupt Controller☆44Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V Nox core☆69Updated 4 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- ☆110Updated last month
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated last week
- Mathematical Functions in Verilog☆95Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Control and status register code generator toolchain☆156Updated last week
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- Labs to learn SpinalHDL☆151Updated last year
- UART models for cocotb☆32Updated 3 months ago
- SystemVerilog synthesis tool☆220Updated 9 months ago