Re-coded Xilinx primitives for Verilator use
☆56Jun 24, 2025Updated last year
Alternatives and similar repositories for verilator_xilinx
Users that are interested in verilator_xilinx are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 4 years ago
- ☆14Mar 27, 2026Updated 7 months ago
- Re-coded Gowin GW1N primitives for Verilator use☆24Aug 19, 2022Updated 4 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 6 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆24Apr 16, 2023Updated 3 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 5 months ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 4 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- CLI for WaveDrom☆68Feb 22, 2024Updated 2 years ago
- Raptor end-to-end FPGA Compiler and GUI☆101Dec 11, 2024Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆104Mar 6, 2022Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Recommended coding standard of Verilog and SystemVerilog.☆37Oct 21, 2021Updated 5 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- Solving Sudokus using open source formal verification tools☆18Aug 16, 2022Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- Sample rate conversion library☆15Apr 13, 2026Updated 6 months ago
- iDEA FPGA Soft Processor☆17Jun 9, 2016Updated 10 years ago
- general-cores☆21Jul 16, 2025Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆36Jul 15, 2024Updated 2 years ago
- FPGA and Digital ASIC Build System☆87Oct 27, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Xilinx Unisim Library in Verilog☆93Jul 22, 2020Updated 6 years ago
- The RIFFA development repository (development fork)☆10Jun 11, 2024Updated 2 years ago
- Qfsm is a graphical tool for designing finite state machine, written in C++ using the Qt library☆11Nov 19, 2018Updated 7 years ago
- ☆24Feb 15, 2023Updated 3 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆31Mar 29, 2013Updated 13 years ago
- An abstraction library for interfacing EDA tools☆803Sep 15, 2026Updated last month
- ☆30Jul 25, 2026Updated 3 months ago
- A tool for modeling FSMs by VHDL or Verilog☆15Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆30Mar 27, 2025Updated last year
- A simple DDR3 memory controller☆68Aug 20, 2026Updated 2 months ago
- ☆17May 20, 2026Updated 5 months ago
- ☆16Jan 19, 2024Updated 2 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 9 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆80Jul 14, 2026Updated 3 months ago