Alternatives and similar repositories for verilator_xilinx:

Users that are interested in verilator_xilinx are comparing it to the libraries listed below

• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆58Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 2 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆33Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated 2 weeks ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆87Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 3 months ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆87Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆61Updated 4 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆169Updated last week
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆51Updated this week
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 weeks ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆91Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 5 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆88Updated 3 years ago