fredrequin / verilator_xilinx

Related projects: ⓘ

• taneroksuz / fpu
  IEEE 754 floating point library in system-verilog and vhdl
  ☆53Updated 3 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆51Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆38Updated 3 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆34Updated 4 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆27Updated 6 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆85Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆59Updated 2 weeks ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆29Updated 3 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆94Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆68Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆49Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆57Updated 5 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆126Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆115Updated this week
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆44Updated 4 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆49Updated 4 years ago
• sequencer / arithmetic
  ☆31Updated 7 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆29Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆53Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆62Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 4 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 4 months ago
• aignacio / nox
  RISC-V Nox core
  ☆59Updated last month
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆75Updated 5 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆23Updated 9 years ago