Giftwen / CourseDigitalICLinks
国科大高等数字集成电路分析与设计课程2022fall
☆25Updated 2 years ago
Alternatives and similar repositories for CourseDigitalIC
Users that are interested in CourseDigitalIC are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 9 months ago
- verilog实现systolic array及配套IO☆8Updated 6 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆86Updated 3 years ago
- ☆111Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- syn script for DC Compiler☆13Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- IC implementation of Systolic Array for TPU☆247Updated 7 months ago
- ☆39Updated 4 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- AXI总线连接器☆97Updated 5 years ago
- CPU Design Based on RISCV ISA☆111Updated 11 months ago
- Collect some IC textbooks for learning.☆143Updated 2 years ago
- COMS 超大规模集成电路设计书籍☆23Updated 3 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆48Updated 3 months ago
- ☆159Updated last month
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- IC implementation of TPU☆125Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆179Updated last year
- 北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】☆36Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆156Updated 3 weeks ago
- ☆70Updated 4 years ago
- Some useful documents of Synopsys☆73Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆94Updated 3 weeks ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago