Giftwen / CourseDigitalIC
国科大高等数字集成电路分析与设计课程2022fall
☆25Updated 2 years ago
Alternatives and similar repositories for CourseDigitalIC:
Users that are interested in CourseDigitalIC are comparing it to the libraries listed below
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆82Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆91Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- CPU Design Based on RISCV ISA☆99Updated 9 months ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆69Updated last week
- Collect some IC textbooks for learning.☆127Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆41Updated 7 months ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆158Updated 4 months ago
- AXI协议规范中文翻译版☆141Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆14Updated 10 months ago
- 北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】☆31Updated 3 years ago
- syn script for DC Compiler☆12Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆184Updated last year
- ☆104Updated 4 years ago
- IC implementation of Systolic Array for TPU☆207Updated 5 months ago
- AXI总线连接器☆96Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆94Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆179Updated 7 years ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- ☆80Updated last month
- ☆66Updated 4 years ago
- ☆133Updated last month
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆41Updated 3 weeks ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆22Updated 2 months ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆139Updated last month
- AXI DMA 32 / 64 bits☆109Updated 10 years ago