FDUCSLG / Arch-2022Spring-FDU
☆10Updated 2 years ago
Related projects: ⓘ
- Introduction to Computer Systems (II), Spring 2021☆46Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆44Updated 9 months ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆10Updated 5 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆14Updated 3 years ago
- NUDT 高级体系结构实验☆27Updated 5 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 3 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆34Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆28Updated last year
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆23Updated 3 years ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Updated 3 years ago
- ☆26Updated 11 months ago
- MIT6.175 & MIT6.375 Study Notes☆23Updated last year
- ☆54Updated 2 months ago
- ☆19Updated last year
- ☆17Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆65Updated last year
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆22Updated 4 years ago
- ☆18Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆41Updated 4 years ago
- 我的一生一芯项目☆16Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 5 months ago
- ☆40Updated 2 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆120Updated 2 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆15Updated 3 years ago
- 中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业☆14Updated 2 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆22Updated last month
- gem5 FS模式实验手册☆28Updated last year
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆13Updated 3 months ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆10Updated 4 years ago