atfox272 / AXI4-Interconnect
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
☆12Updated 2 months ago
Alternatives and similar repositories for AXI4-Interconnect
Users that are interested in AXI4-Interconnect are comparing it to the libraries listed below
Sorting:
- ☆33Updated 6 years ago
- ☆22Updated 2 years ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- This is a simple Risc-v core for software simulation on FPGA.☆8Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- General Purpose AXI Direct Memory Access☆49Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆48Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 6 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- HYF's high quality verilog codes☆12Updated 4 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- ☆27Updated 4 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- understanding of cocotb (In Chinese Only)☆17Updated last year
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated this week
- Complete tutorial code.☆20Updated last year
- ☆27Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago