atfox272 / AXI4-InterconnectLinks
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
☆24Updated 11 months ago
Alternatives and similar repositories for AXI4-Interconnect
Users that are interested in AXI4-Interconnect are comparing it to the libraries listed below
Sorting:
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Updated 10 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆20Updated 3 years ago
- ☆31Updated 5 years ago
- ☆33Updated 2 months ago
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- CORE-V MCU UVM Environment and Test Bench☆26Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Updated 3 years ago
- Andes Vector Extension support added to riscv-dv☆18Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆14Updated 11 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- 第四届全国大学生嵌入式比赛SoC☆11Updated 3 years ago
- ☆40Updated 6 years ago
- ☆15Updated 3 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆28Updated 3 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Updated 2 months ago
- Direct Access Memory for MPSoC☆13Updated 2 weeks ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- A Verilog implementation of a processor cache.☆36Updated 8 years ago
- ☆11Updated 5 years ago
- ☆13Updated 4 years ago