AXI协议规范中文翻译版
☆171Jul 5, 2022Updated 3 years ago
Alternatives and similar repositories for AXI_spec_chinese
Users that are interested in AXI_spec_chinese are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- verilog module add prefix script 可用于ysyx项目添加学号☆13Mar 4, 2024Updated 2 years ago
- ☆22Apr 16, 2023Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆127Aug 29, 2022Updated 3 years ago
- ☆64Sep 23, 2022Updated 3 years ago
- This is DreamOS C Version by lizhirui since 2021-05-18☆10Aug 23, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆798Sep 14, 2023Updated 2 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。☆142Jan 26, 2024Updated 2 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆27Dec 17, 2022Updated 3 years ago
- ☆94Sep 30, 2025Updated 5 months ago
- ☆93Nov 12, 2025Updated 4 months ago
- An uvm verification env for ahb2apb bridge☆57Apr 9, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆19May 1, 2023Updated 2 years ago
- Must-have verilog systemverilog modules☆37May 1, 2022Updated 3 years ago
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- ☆73Apr 23, 2023Updated 2 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- AXI总线连接器☆105Mar 26, 2020Updated 6 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆53Dec 18, 2025Updated 3 months ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆607Sep 15, 2023Updated 2 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆433Sep 14, 2023Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,787Aug 6, 2025Updated 7 months ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆12Aug 21, 2023Updated 2 years ago
- Vivado诸多IP，包括图像处理等☆235Jul 28, 2024Updated last year
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆122Sep 19, 2024Updated last year
- ☆12Jul 20, 2022Updated 3 years ago
- Must-have verilog systemverilog modules☆1,942Mar 12, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- ☆29Jun 19, 2025Updated 9 months ago
- ☆21May 26, 2025Updated 10 months ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago
- A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame.☆57Jun 7, 2025Updated 9 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆84Aug 29, 2023Updated 2 years ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆631Aug 13, 2024Updated last year