Alternatives and similar repositories for AXI_spec_chinese

Users that are interested in AXI_spec_chinese are comparing it to the libraries listed below

• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆113Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆98Updated 5 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆121Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• RV-BOSC / OpenNoC
  ☆163Updated last month
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆116Updated 12 years ago
• RongyeL / EasyAXI
  ☆44Updated last month
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆48Updated 10 months ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year
• ForrestBlue / cortexm0ds
  ☆65Updated 9 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆89Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆207Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆75Updated 3 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆146Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆180Updated 7 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆145Updated 3 weeks ago
• Advanced-Microelectronics-Group / OpenC910_Modified
  commit rtl and build cosim env
  ☆35Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆118Updated last month
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆190Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆67Updated 5 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago