Alternatives and similar repositories for AXI_spec_chinese

Users that are interested in AXI_spec_chinese are comparing it to the libraries listed below

• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 5 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆120Updated last year
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆169Updated this week
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• RV-BOSC / OpenNoC
  ☆184Updated 2 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆214Updated 2 years ago
• RongyeL / EasyAXI
  ☆56Updated 2 weeks ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆94Updated 3 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆202Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆123Updated 2 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆54Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆64Updated 6 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆155Updated 3 years ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆35Updated 6 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆176Updated 7 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 3 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆148Updated this week
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆191Updated 9 months ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆80Updated 3 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆119Updated 12 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆25Updated 2 years ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆107Updated 2 weeks ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆20Updated last year
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆74Updated 3 years ago