lizhirui / DreamCoreLinks
☆64Updated 3 years ago
Alternatives and similar repositories for DreamCore
Users that are interested in DreamCore are comparing it to the libraries listed below
Sorting:
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- ☆92Updated 4 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆219Updated 7 months ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- ☆90Updated 2 months ago
- ☆19Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- ☆71Updated this week
- ☆47Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆138Updated 11 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆150Updated last year
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Pick your favorite language to verify your chip.☆77Updated this week
- ☆58Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- ☆22Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆89Updated last year
- Various caches written in Verilog-HDL☆127Updated 10 years ago
- ☆72Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆225Updated 2 months ago
- ☆32Updated 6 months ago