lizhirui / DreamCore

Related projects ⓘ

Alternatives and complementary repositories for DreamCore

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆132Updated 2 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆107Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆62Updated 3 months ago
• OSCPU / ysyxSoC
  ☆76Updated 2 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆37Updated 4 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆36Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆55Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆123Updated last week
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆91Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆56Updated 10 months ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆31Updated 3 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆129Updated 5 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆68Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆46Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆47Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (deflate) compressor, which input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压…
  ☆100Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆76Updated 5 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆110Updated 4 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆199Updated 4 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 5 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• OSCPU / yosys-sta
  ☆43Updated 4 months ago
• zion-group / VerilogCodingStyle
  ☆58Updated 4 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆35Updated 6 years ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆70Updated 3 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆102Updated 11 years ago