splinedrive / KianV-RV32IMA-RISC-V-uLinux-SoCLinks
☆18Updated 4 months ago
Alternatives and similar repositories for KianV-RV32IMA-RISC-V-uLinux-SoC
Users that are interested in KianV-RV32IMA-RISC-V-uLinux-SoC are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- RISC-V Nox core☆71Updated 6 months ago
- ☆58Updated 10 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated 2 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆135Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Naive Educational RISC V processor☆94Updated 3 months ago
- Raptor end-to-end FPGA Compiler and GUI☆95Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆56Updated last week
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Updated 2 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆33Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- The multi-core cluster of a PULP system.☆111Updated this week
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 2 weeks ago
- Simple runtime for Pulp platforms☆50Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- ☆60Updated 4 years ago