thu-cs-lab / verilog-coding-standardLinks
Recommended coding standard of Verilog and SystemVerilog.
☆36Updated 4 years ago
Alternatives and similar repositories for verilog-coding-standard
Users that are interested in verilog-coding-standard are comparing it to the libraries listed below
Sorting:
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆37Updated 3 years ago
- Yet another toy CPU.☆93Updated 2 years ago
- CQU Dual Issue Machine☆38Updated last year
- 龙芯杯21个人赛作品☆36Updated 4 years ago
- 给NEMU移植Linux Kernel!☆21Updated 6 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- A Flexible Cache Architectural Simulator☆16Updated 3 months ago
- ☆22Updated last month
- ☆25Updated 2 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Updated last year
- MIT6.175 & MIT6.375 Study Notes☆45Updated 2 years ago
- QuardStar Tutorial is all you need !☆18Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆50Updated 2 months ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- ☆35Updated 6 years ago
- Introduction to Computer Systems (II), Spring 2021☆52Updated 4 years ago
- My knowledge base☆74Updated this week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 3 weeks ago
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆82Updated 2 weeks ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…☆27Updated last year
- A small RISC-V kernel coding by C, tested on sifive unmatched board.☆16Updated 3 years ago
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10Updated 4 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- PA + Labs for Operating Systems 2019 course in NJU taught by JYY.☆12Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆78Updated 2 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago