Recommended coding standard of Verilog and SystemVerilog.
☆37Oct 21, 2021Updated 4 years ago
Alternatives and similar repositories for verilog-coding-standard
Users that are interested in verilog-coding-standard are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CIDR union / subtraction☆14Updated this week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Plagiarism detection tool in Rust (inspired by Stanford Moss)☆54Jun 28, 2026Updated 3 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- Pipelined MIPS CPU（course assignment for BUAA-Computer-Organization）☆22Feb 5, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Jul 14, 2026Updated last week
- CV32E40X Design-Verification environment☆18Jun 2, 2026Updated last month
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆41Jan 26, 2022Updated 4 years ago
- ☆16Mar 18, 2025Updated last year
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 2 months ago
- My knowledge base☆102Updated this week
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 10 months ago
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 3 years ago
- Tsinghua Advanced Networking Labs on FPGA☆40Oct 24, 2024Updated last year
- ☆12Jul 3, 2018Updated 8 years ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- ☆22Nov 3, 2025Updated 8 months ago
- 计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位☆127Dec 4, 2025Updated 7 months ago
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 4 years ago
- 重庆大学Beamer模板 --- CQUBeamerTemplate☆16May 7, 2018Updated 8 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆10Sep 23, 2023Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆95Aug 29, 2023Updated 2 years ago
- Introduction to homotopy type theory (reading course), LP2 2023, offered via DAT235/DIT577: Research-oriented course in Computer Science …☆14Apr 17, 2024Updated 2 years ago
- Build edk2 development and debugging environment under win10, for recording some notes and writing self tools.☆13Aug 14, 2022Updated 3 years ago
- My Curriculum Vitae and Resume☆16Jul 14, 2024Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- ☆14Apr 28, 2026Updated 2 months ago
- A naive verilog/systemverilog formatter☆22Apr 2, 2026Updated 3 months ago
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)☆23Aug 21, 2018Updated 7 years ago
- Tracker for books I've read. Looking for suggestion and inspirational for others. :)☆14May 3, 2026Updated 2 months ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Jan 26, 2020Updated 6 years ago
- ☆10Mar 19, 2015Updated 11 years ago
- Make UEFI (BIOS) Setup IFR dumps easy to read, browse and use with UEFI Variable Tool☆16Nov 20, 2023Updated 2 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆27Mar 8, 2026Updated 4 months ago