tactcomplabs / revLinks
RISC-V SST CPU Component
☆24Updated last week
Alternatives and similar repositories for rev
Users that are interested in rev are comparing it to the libraries listed below
Sorting:
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ordspecsim: The Swarm architecture simulator☆25Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- ☆92Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆36Updated last month
- ☆13Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆59Updated this week
- ☆87Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Fast and accurate DRAM power and energy estimation tool☆169Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- ☆30Updated 9 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 7 months ago
- ☆33Updated 4 months ago
- The OpenPiton Platform☆29Updated 2 years ago
- Public release☆57Updated 5 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 weeks ago
- DASS HLS Compiler☆29Updated last year
- CGRA framework with vectorization support.☆34Updated this week
- Next generation CGRA generator☆113Updated last week