watz0n / learn-rv32i-asapLinks
A Simple As Possible RISCV-32I core with debug module.
☆42Updated 6 years ago
Alternatives and similar repositories for learn-rv32i-asap
Users that are interested in learn-rv32i-asap are comparing it to the libraries listed below
Sorting:
- Chisel Learning Journey☆111Updated 2 years ago
- Provides various testers for chisel users☆100Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- ☆82Updated last year
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- ☆89Updated 4 months ago
- Hardware design with Chisel☆35Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- ☆51Updated last week
- A teaching-focused RISC-V CPU design used at UC Davis☆153Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- chipyard in mill :P☆77Updated 2 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- A Tiny Processor Core☆114Updated 6 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- RISC-V architecture concurrency model litmus tests☆96Updated this week
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Chisel components for FPGA projects☆128Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆106Updated last month
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago