soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk contained in the SPI flash.
☆34Dec 11, 2016Updated 9 years ago
Alternatives and similar repositories for sp-i586
Users that are interested in sp-i586 are comparing it to the libraries listed below
Sorting:
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Feb 23, 2020Updated 6 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆15Oct 15, 2016Updated 9 years ago
- Porting of (JavaScript version of) corewars8086 from codeguru xtreme to RISC-V cpu☆14Mar 25, 2019Updated 6 years ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Feb 16, 2013Updated 13 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- 串口通过9个元件转换为SWD接口☆14Feb 16, 2026Updated 3 weeks ago
- Misc iCE40 specific cores☆14Feb 13, 2023Updated 3 years ago
- ☆17Aug 21, 2023Updated 2 years ago
- The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.☆404Aug 19, 2014Updated 11 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated 11 months ago
- Cross platform, open source IC layout editor☆16Oct 26, 2025Updated 4 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆187Mar 10, 2024Updated last year
- Verilog clone of YM2149☆43Feb 1, 2025Updated last year
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- Completed LDO Design for Skywaters 130nm☆19Feb 16, 2023Updated 3 years ago
- Interfaz directa con teclados USB en Verilog con control de los Leds de teclado y conversión a PS/2.☆18Feb 26, 2022Updated 4 years ago
- 80186 compatible SystemVerilog CPU core and FPGA reference design☆409Mar 22, 2024Updated last year
- 4004 CPU and MCS-4 family chips☆45Jul 17, 2014Updated 11 years ago
- Experimental pipelined 4502 CPU design☆21Nov 29, 2017Updated 8 years ago
- RISC-V port of LLVM Linker☆24Aug 3, 2018Updated 7 years ago
- Tiny PicoProbe PCB☆25Feb 25, 2023Updated 3 years ago
- Yet another Ascii Art generator and player that is highly configurable, chooses most suitable letter and colour totally by itself☆19Feb 2, 2019Updated 7 years ago
- Acorn BBC Micro on an Altera DE1 FPGA board☆25Jan 13, 2016Updated 10 years ago
- Verilog re-implementation of the famous CAPCOM arcade game☆29Jan 25, 2019Updated 7 years ago
- Hardware design of the MCH2022 badge☆26Nov 10, 2022Updated 3 years ago
- Propeller 1 design and example files to be run on FPGA boards.☆22Jul 29, 2019Updated 6 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆62Jan 12, 2021Updated 5 years ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆25May 22, 2022Updated 3 years ago
- Submission template for TT02☆25Feb 2, 2023Updated 3 years ago
- buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"☆26Apr 23, 2024Updated last year
- The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.☆79Mar 11, 2012Updated 13 years ago
- Small microcoded 68000 verilog softcore☆59Oct 30, 2018Updated 7 years ago
- IBM-PC clone based on an Intel 80386SX processor and an Altera Cyclone IV☆70Oct 15, 2016Updated 9 years ago
- Port of EmuTOS to the ARM architecture.☆27May 25, 2021Updated 4 years ago
- The Zylin ZPU☆249Apr 21, 2015Updated 10 years ago
- RGB video input for Altera DE1 board + PAL Modulator☆27May 15, 2023Updated 2 years ago
- Skywater 130nm Klayout Device Generators PDK☆30Jul 12, 2024Updated last year
- ☆33Jul 28, 2020Updated 5 years ago
- Misc Atari ST stuff☆32Jan 6, 2021Updated 5 years ago