antmicro / verilator
Verilator open-source SystemVerilog simulator and lint system
☆20Updated this week
Alternatives and similar repositories for verilator:
Users that are interested in verilator are comparing it to the libraries listed below
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 9 months ago
- ☆22Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- ☆22Updated 8 years ago
- ☆33Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆31Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- ☆43Updated 5 years ago
- hardware library for hwt (= ipcore repo)☆37Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- An implementation of RISC-V☆30Updated 3 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆34Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆41Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last month
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆54Updated last month
- UVM Python Verification Agents Library☆14Updated 4 years ago
- ☆13Updated 4 years ago
- ☆36Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Hardware Verification library for C++, SystemC and SystemVerilog☆30Updated 12 years ago