antmicro / verilator
Verilator open-source SystemVerilog simulator and lint system
☆20Updated this week
Related projects ⓘ
Alternatives and complementary repositories for verilator
- Extended and external tests for Verilator testing☆15Updated 2 weeks ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆22Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆78Updated last month
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 3 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- hardware library for hwt (= ipcore repo)☆34Updated 2 weeks ago
- ☆39Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆43Updated 3 months ago
- Announcements related to Verilator☆38Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- UVM Python Verification Agents Library☆13Updated 3 years ago
- ☆30Updated last year
- Common SystemVerilog RTL modules for RgGen☆11Updated 5 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- ☆36Updated 2 years ago
- Open FPGA Modules☆22Updated last month
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- Doxygen with verilog support☆36Updated 5 years ago
- Extensible FPGA control platform☆53Updated last year
- SoCRocket - Core Repository☆33Updated 7 years ago
- ☆32Updated last year
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆15Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- RISC-V soft-core PEs for TaPaSCo☆15Updated 4 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year