Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
☆14Jun 9, 2021Updated 5 years ago
Alternatives and similar repositories for RTL-PowerOptimization
Users that are interested in RTL-PowerOptimization are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated 11 months ago
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆23Nov 9, 2025Updated 8 months ago
- A web app that lively plots data from a Firebase Realtime Database node, thanks to plotly.js☆15Dec 17, 2018Updated 7 years ago
- Bugs Everywhere (BE), a bugtracker built on distributed version control.☆17Nov 17, 2016Updated 9 years ago
- Computer architecture project : Cache simulator with LRU replacement policy☆12Jul 27, 2021Updated 4 years ago
- Programming (8051)☆11Nov 23, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Dec 8, 2022Updated 3 years ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Apr 10, 2026Updated 3 months ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Aug 23, 2021Updated 4 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 7 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- WSL Ubuntu Dotfiles☆29Dec 1, 2023Updated 2 years ago
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 8 months ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- Introductory course into static timing analysis (STA).☆112Jul 6, 2025Updated last year
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆17Mar 3, 2018Updated 8 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Antelope cryptography library for ECC, RSA and SHA-3☆10Mar 12, 2025Updated last year
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.☆13Mar 24, 2017Updated 9 years ago
- ☆11Mar 3, 2025Updated last year
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆21Jun 14, 2026Updated last month
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- ☆34Mar 4, 2024Updated 2 years ago