Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
☆14Jun 9, 2021Updated 4 years ago
Alternatives and similar repositories for RTL-PowerOptimization
Users that are interested in RTL-PowerOptimization are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 8 months ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Feb 18, 2021Updated 5 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- Bugs Everywhere (BE), a bugtracker built on distributed version control.☆16Nov 17, 2016Updated 9 years ago
- Computer architecture project : Cache simulator with LRU replacement policy☆12Jul 27, 2021Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated 11 months ago
- Custom ASIC Design for SHA-256☆13Nov 22, 2025Updated 4 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 6 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Dec 8, 2022Updated 3 years ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Updated this week
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Aug 23, 2021Updated 4 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 5 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ECG Classification using PyTorch☆18Jun 27, 2022Updated 3 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- 基于玄铁openc906,搭建最小化SoC系统☆20Apr 7, 2025Updated last year
- A pipelined brainfuck softcore in Verilog☆19Aug 5, 2014Updated 11 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆23Jun 30, 2025Updated 9 months ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 4 years ago
- Introductory course into static timing analysis (STA).☆106Jul 6, 2025Updated 9 months ago
- ☆17Apr 7, 2022Updated 4 years ago
- Antelope cryptography library for ECC, RSA and SHA-3☆10Mar 12, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Aug 19, 2024Updated last year
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆17Jun 11, 2025Updated 10 months ago
- ☆16Mar 27, 2024Updated 2 years ago
- Terminal.app configuration handling Fn keys right☆21Nov 13, 2017Updated 8 years ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 3 months ago