Alternatives and similar repositories for abc

Users that are interested in abc are comparing it to the libraries listed below

• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated last month
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆112Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last month
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated this week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 11 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated 3 weeks ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆30Updated last month
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆86Updated 2 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 4 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last month
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆33Updated last year
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 2 months ago