YosysHQ / abcLinks
ABC: System for Sequential Logic Synthesis and Formal Verification
☆30Updated last week
Alternatives and similar repositories for abc
Users that are interested in abc are comparing it to the libraries listed below
Sorting:
- A Verilog Synthesis Regression Test☆37Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- Example of how to use UVM with Verilator☆28Updated last week
- FPGA Assembly (FASM) Parser and Generator☆98Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 6 months ago
- IRSIM switch-level simulator for digital circuits☆35Updated last month
- Experiments with Yosys cxxrtl backend☆50Updated 10 months ago
- PicoRV☆43Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- A reimplementation of a tiny stack CPU☆85Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- A bit-serial CPU☆19Updated 6 years ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆112Updated 2 years ago
- This repository contain source code for ngspice and ghdl integration☆33Updated 11 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- A pipelined RISC-V processor☆62Updated 2 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆58Updated 3 years ago
- The specification for the FIRRTL language☆62Updated last week
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated last month
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago