ABC: System for Sequential Logic Synthesis and Formal Verification
☆33Jul 9, 2026Updated 2 weeks ago
Alternatives and similar repositories for abc
Users that are interested in abc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- GUI for SymbiYosys☆17Jul 16, 2026Updated last week
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Bare-bones demo of full-duplex I2S with the RP2040 and the WM8731 codec☆12Oct 29, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆17Nov 25, 2017Updated 8 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆32Jan 17, 2020Updated 6 years ago
- A normalizing interpreter for the untyped λ-calculus in 292 characters of Haskell☆11Mar 8, 2016Updated 10 years ago
- Project Trellis database☆13Sep 15, 2025Updated 10 months ago
- download the macOS SDK legally without an Apple account☆12Jun 1, 2023Updated 3 years ago
- Documenting the Lattice ECP5 bit-stream format.☆463May 9, 2026Updated 2 months ago
- Mutation Cover with Yosys (MCY)☆96Jul 9, 2026Updated 2 weeks ago
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆19Oct 7, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- Yet Another VHDL tool☆30May 15, 2017Updated 9 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- batch eval tool for machine code. eval() but for asm.☆12Dec 31, 2022Updated 3 years ago
- Wishbone SATA Controller☆28Jul 9, 2026Updated 2 weeks ago
- ☆15May 11, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- fundamental traits to describe an architecture in the yaxpeax project☆18Mar 1, 2025Updated last year
- nextpnr portable FPGA place and route tool☆1,711Updated this week
- STM32 BluePill as USB SD Card reader in SPI mode with SPL☆13Jan 11, 2022Updated 4 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- 6809 Playground - main system☆10Jul 12, 2025Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆533Jul 16, 2026Updated last week
- A reimplementation of a tiny stack CPU☆89Dec 8, 2023Updated 2 years ago
- ☆17Apr 14, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆32Jul 12, 2024Updated 2 years ago
- Naive Educational RISC V processor☆96Oct 12, 2025Updated 9 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 19, 2026Updated 4 months ago
- User-space C driver for Joulescope™ products☆16Updated this week
- converts catgirls to gds files☆15May 24, 2021Updated 5 years ago
- Firmware for Alpha emulation under QEMU☆13Jun 15, 2021Updated 5 years ago
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆17Sep 3, 2025Updated 10 months ago