lnestor / sat_attackLinks
A basic implementation of a SAT attack on logic locking.
☆12Updated 4 years ago
Alternatives and similar repositories for sat_attack
Users that are interested in sat_attack are comparing it to the libraries listed below
Sorting:
- This is a probabilistic SAT attack tool.☆14Updated 4 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆36Updated 2 weeks ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- ☆17Updated last year
- This is a python repo for flattening Verilog☆19Updated 3 months ago
- TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection☆21Updated last year
- Lock circuitgraphs using various logic locking techniques☆10Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- ☆74Updated 2 months ago
- Circuit release of the MAGICAL project☆36Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 7 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- ☆25Updated 4 years ago
- EDA physical synthesis optimization kit☆60Updated last year
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆31Updated last year
- GPU-based logic synthesis tool☆90Updated 3 weeks ago
- ☆33Updated 5 years ago
- ☆53Updated 3 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- DATC RDF☆50Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- ☆31Updated 3 years ago
- ☆44Updated 5 years ago
- Tools for working with circuits as graphs in python☆122Updated last year
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆55Updated 7 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago