A basic implementation of a SAT attack on logic locking.
☆13Jun 30, 2021Updated 4 years ago
Alternatives and similar repositories for sat_attack
Users that are interested in sat_attack are comparing it to the libraries listed below
Sorting:
- This is a probabilistic SAT attack tool.☆13Jun 5, 2021Updated 4 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- ☆23Mar 13, 2023Updated 2 years ago
- ☆21Jan 25, 2018Updated 8 years ago
- Hardware Security Labs☆31May 3, 2017Updated 8 years ago
- ☆11Nov 10, 2025Updated 3 months ago
- ☆16Nov 8, 2024Updated last year
- This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. …☆21Mar 25, 2025Updated 11 months ago
- HELM: Navigating Homomorphic Encryption through Gates and Lookup Tables☆11Apr 7, 2025Updated 10 months ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- Proof-of-concept implementation for the paper "Homomorphic Encryption for Large Integers from Nested Residue Number Systems", presented a…☆27Jun 4, 2025Updated 8 months ago
- CrazyDiskInfo is an interactive TUI S.M.A.R.T viewer for Unix systems.☆10Aug 9, 2022Updated 3 years ago
- Used for hardware trojan detection(Based on Trust_Hub)☆10Jul 30, 2019Updated 6 years ago
- Debiasing Through Data Attribution☆12May 23, 2024Updated last year
- WebRTCを使ってブラウザ間通信を行うオンセツール ユドナリウムの変更版ユドナリウムリリィです☆18Jan 22, 2026Updated last month
- A WIP library to control B1500 and similar testers via the VISA protocol, built on pyvisa☆11Nov 4, 2016Updated 9 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- BuDDy BDD package (with CMake support)☆15May 7, 2024Updated last year
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆12Apr 6, 2025Updated 10 months ago
- 基于tenserflow2.10与yolo v4开发的目标检测、测距、避障提示☆14Dec 23, 2023Updated 2 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆13Apr 1, 2020Updated 5 years ago
- Quantized training method for RRAM-based systems.☆12Sep 24, 2018Updated 7 years ago
- Stencila for Python☆17Aug 3, 2018Updated 7 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- A library for lattice-based homomorphic encryption in Go☆14May 15, 2022Updated 3 years ago
- ☆12Apr 25, 2025Updated 10 months ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆27Sep 9, 2025Updated 5 months ago
- Defense/Attack PUF Library (DA PUF Library)☆55May 5, 2020Updated 5 years ago
- Skeleton (but pronounced like Peloton): A Zero-Click RCE exploit for CVE-2021-0326☆20Mar 16, 2022Updated 3 years ago
- ASM generation tool for GAS/NASM/MASM with Xbyak-like syntax in Python☆12Nov 10, 2025Updated 3 months ago
- Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.☆15May 17, 2018Updated 7 years ago
- [NeurIPS'24] "NeuralFuse: Learning to Recover the Accuracy of Access-Limited Neural Network Inference in Low-Voltage Regimes"☆10Sep 18, 2025Updated 5 months ago
- A modular library for designing and optimising homomorphic encryption schemes☆24Feb 6, 2026Updated 3 weeks ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 2 months ago
- [ICLR 2025] On Evluating the Durability of Safegurads for Open-Weight LLMs☆13Jun 20, 2025Updated 8 months ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 3 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 7 months ago