Alternatives and similar repositories for sat_attack:

Users that are interested in sat_attack are comparing it to the libraries listed below

• DfX-NYUAD / PSAT
  This is a probabilistic SAT attack tool.
  ☆12Updated 3 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆24Updated 5 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆30Updated last week
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆37Updated 2 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆15Updated 3 weeks ago
• Yu-Maryland / Verilog-to-PyG
  ☆23Updated 9 months ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆28Updated 2 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆41Updated 2 weeks ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆49Updated last year
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆40Updated last year
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆34Updated 2 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆48Updated 3 weeks ago
• DfX-NYUAD / GNNUnlock
  ☆14Updated 2 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• aolofsson / IDEA
  ☆32Updated 5 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆39Updated 4 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆33Updated 7 months ago
• nputikhin / sat_atpg
  SAT-based ATPG using TG-Pro model
  ☆15Updated 6 years ago
• vaughnbetz / COFFE
  ☆39Updated 4 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 2 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆17Updated 2 years ago
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 3 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆29Updated last year
• zshi0616 / python-deepgate
  ☆21Updated 7 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆79Updated 6 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 2 months ago