berkeley-abc / abc-zz
Niklas Een's ABC/ZZ framework
☆22Updated 2 years ago
Alternatives and similar repositories for abc-zz:
Users that are interested in abc-zz are comparing it to the libraries listed below
- Optimization results for superconducting electronic (SCE) circuits☆13Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- AIGER And-Inverter-Graph Library☆74Updated 3 weeks ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆103Updated 5 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆57Updated 11 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- A logic synthesis tool☆73Updated 3 weeks ago
- Coriolis VLSI EDA Tool (LIP6)☆64Updated this week
- DATC RDF☆50Updated 4 years ago
- An advanced header-only exact synthesis library☆25Updated 2 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆36Updated 10 months ago
- IDEA project source files☆106Updated 5 months ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆29Updated 9 months ago
- C++ truth table library☆53Updated last year
- An infrastructure for integrated EDA☆39Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆26Updated 5 years ago
- Qrouter detail router for digital ASIC designs☆57Updated 3 weeks ago
- Power grid analysis☆19Updated 4 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆76Updated 10 months ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- A parallel global router using the Galois framework☆27Updated last year
- Parsing library for BLIF netlists☆18Updated 6 months ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago