Alternatives and similar repositories for abc-zz

Users that are interested in abc-zz are comparing it to the libraries listed below

• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆86Updated last month
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• lsils / kitty
  C++ truth table library
  ☆59Updated last month
• msoeken / cirkit
  A circuit toolkit
  ☆105Updated 5 years ago
• lsils / mockturtle
  C++ logic network library
  ☆247Updated 3 weeks ago
• nbulsi / also
  A logic synthesis tool
  ☆78Updated last month
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• stdgregwar / elve
  ELVE : ELVE Logic Visualization Engine
  ☆11Updated 8 years ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆14Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆111Updated 3 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆51Updated last month
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 3 weeks ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆195Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 4 months ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆43Updated last week
• lnis-uofu / ML-Mapper
  ☆11Updated 2 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆16Updated 8 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 10 months ago