☆59Jun 3, 2025Updated 9 months ago
Alternatives and similar repositories for chiplet-network-sim
Users that are interested in chiplet-network-sim are comparing it to the libraries listed below
Sorting:
- A toolchain for rapid design space exploration of chiplet architectures☆75Jul 25, 2025Updated 7 months ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆63Mar 17, 2025Updated 11 months ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 4 years ago
- Cost Model☆19Apr 11, 2025Updated 10 months ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆110Apr 28, 2025Updated 10 months ago
- A list of our chiplet simulaters☆48Jun 22, 2025Updated 8 months ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- The wafer-native AI accelerator simulation platform and inference engine.☆50Jan 1, 2026Updated 2 months ago
- BookSim 2.0☆404Jun 24, 2024Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆75Jun 30, 2024Updated last year
- ☆35Jul 9, 2020Updated 5 years ago
- ☆33Dec 11, 2025Updated 2 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆189Jan 8, 2026Updated last month
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Jun 27, 2024Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- ☆14Oct 11, 2024Updated last year
- Distributed SDDMM Kernel☆12Jul 8, 2022Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- ☆41Jun 30, 2025Updated 8 months ago
- ☆29Aug 4, 2025Updated 7 months ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 10 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- Implementation of the PCIe physical layer☆61Jul 11, 2025Updated 7 months ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆125Aug 27, 2024Updated last year
- Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm☆16Oct 11, 2020Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- Repository to host and maintain SCALE-Sim code☆417Feb 2, 2026Updated last month
- ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale☆524Jan 3, 2026Updated 2 months ago
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆93Updated this week
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Apr 4, 2024Updated last year
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Apr 18, 2018Updated 7 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 8 months ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Aug 26, 2024Updated last year