High Bandwidth Memory (HBM) timing model based on DRAMSim2
☆45Jul 28, 2017Updated 8 years ago
Alternatives and similar repositories for HBM
Users that are interested in HBM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆60Sep 30, 2019Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Jun 30, 2017Updated 8 years ago
- Fast and accurate DRAM power and energy estimation tool☆192Updated this week
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆456Aug 3, 2024Updated last year
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 9 months ago
- Mallacc: Accelerating Memory Allocation☆13Jan 2, 2018Updated 8 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆686Aug 29, 2023Updated 2 years ago
- Processing in Memory Emulation☆24Feb 24, 2023Updated 3 years ago
- BadgerTrap is a tool to instrument x86-64 TLB misses.☆13Nov 13, 2016Updated 9 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago
- hybrid memory simulator consists of MarssX86,DRAMSim2, NVMain and Hybridsim. This simulator has already provided interface to plugin DRAM…☆24Oct 22, 2015Updated 10 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆294Nov 11, 2020Updated 5 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Apr 4, 2024Updated last year
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Jul 29, 2020Updated 5 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆346Mar 9, 2026Updated 2 weeks ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆14Jun 7, 2025Updated 9 months ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Feb 13, 2017Updated 9 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆12Dec 10, 2024Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆182Oct 1, 2022Updated 3 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- An infrastructure for inline acceleration of network applications☆30Oct 25, 2021Updated 4 years ago
- ☆11Mar 14, 2023Updated 3 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆27Dec 18, 2024Updated last year
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆63Aug 11, 2024Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆86Aug 28, 2023Updated 2 years ago