supadupaplex / pfecap
Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET
☆24Updated 5 years ago
Alternatives and similar repositories for pfecap:
Users that are interested in pfecap are comparing it to the libraries listed below
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Hardware Description Library☆79Updated last month
- repository for a bandgap voltage reference in SKY130 technology☆37Updated 2 years ago
- MRAM magnetization simulation framework. s-LLGS python and verilog-a solvers for transients simulation and Fokker-planck equation solver…☆41Updated 2 years ago
- Advanced Integrated Circuits 2024☆25Updated 4 months ago
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆16Updated last week
- AIB Generator: Analog hardware compiler for AIB PHY☆32Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Open source process design kit for 28nm open process☆51Updated 11 months ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 7 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Verilog-A simulation models☆65Updated 2 months ago
- sram/rram/mram.. compiler☆32Updated last year
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆64Updated 2 years ago
- Automated Large-Scale PIC Routing (accepted at ISPD 2025)☆20Updated 2 weeks ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- SKY130 ReRAM and examples (SkyWater Provided)☆37Updated 2 years ago
- ☆16Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- ☆43Updated 11 months ago
- Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations☆13Updated 5 years ago
- Circuit release of the MAGICAL project☆34Updated 5 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated 9 months ago
- MOSIS MPW Test Data and SPICE Models Collections☆33Updated 5 years ago
- ☆22Updated 2 years ago
- ☆27Updated 7 months ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆26Updated 2 years ago