Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET
☆31Feb 16, 2020Updated 6 years ago
Alternatives and similar repositories for pfecap
Users that are interested in pfecap are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A scalable FeFET compact model☆30Apr 21, 2022Updated 4 years ago
- ☆16Nov 18, 2016Updated 9 years ago
- HfO2 Ferroelectric Capacitor VerilogA Compact Model for Circuit Simulation☆17Jul 7, 2026Updated 2 months ago
- Verilog-A simulation models☆118Updated this week
- ☆15Dec 15, 2021Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆47Aug 6, 2020Updated 6 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- ☆21Updated this week
- The ability to manipulate domains and domain walls underpins function in a range of next-generation applications of ferroelectrics. While…☆22Jul 6, 2023Updated 3 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Comprehensive numerical modeling of filamentary RRAM devices including voltage ramp-rate and cycle-to-cycle variations☆26Apr 4, 2024Updated 2 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆26Jan 10, 2022Updated 4 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Python bindings for controlling MPI probe stations☆12Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Cookiecutter template for FastAPI + Panel projects in Python☆10Apr 18, 2022Updated 4 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- STM32 RFID Reader / Writer☆16May 24, 2014Updated 12 years ago
- Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.☆14Dec 5, 2019Updated 6 years ago
- KLayoutPhotonicPCells Core Library. Functionallities to extend KLayout PCells for Photonics☆10Jan 10, 2020Updated 6 years ago
- A wavetable synthesizer in Zig☆13Mar 26, 2020Updated 6 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Ratatoskr NoC Simulator☆30Apr 13, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Web app using Pyodide to demo different types of Scikit-learn classifiers☆13Apr 16, 2022Updated 4 years ago
- MT8816 based 16x16 Analog Switch Matrix☆16Sep 23, 2023Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- A WIP library to control B1500 and similar testers via the VISA protocol, built on pyvisa☆11Nov 4, 2016Updated 9 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14May 26, 2026Updated 3 months ago
- ☆13Dec 9, 2024Updated last year
- Converts GDSII (IC layout database) files to SVG (Vector graphics) files.☆17Feb 10, 2023Updated 3 years ago
- Fully Connected Memristor based Neural Network Simulator☆10Jun 7, 2024Updated 2 years ago
- An innovative Verilog-A compiler☆197Aug 20, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Arduino library to support S2-LP sub-1GHz transceiver☆15May 9, 2023Updated 3 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- ☆15Oct 25, 2021Updated 4 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆16Oct 5, 2025Updated 11 months ago
- MATLAB-based RFID passive Receiver. The decoder takes recorded samples from a reader-tag interaction and decodes the tag's unique ID's or…☆13Jun 3, 2021Updated 5 years ago
- ☆21Jul 2, 2022Updated 4 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 4 years ago