HLS code for Network on Chip (NoC)
☆23Sep 11, 2020Updated 6 years ago
Alternatives and similar repositories for HLS_NoC
Users that are interested in HLS_NoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆20Jul 17, 2019Updated 7 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 12 years ago
- ☆11Jan 25, 2023Updated 3 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- An implementation of Lz77 compression algorithm on FPGA using MaxCompiler programming tool.☆10Sep 4, 2015Updated 11 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 7 years ago
- HLS for Networks-on-Chip☆40Feb 18, 2021Updated 5 years ago
- Network on Chip for MPSoC☆30Updated this week
- ☆27Dec 1, 2020Updated 5 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 10 years ago
- ☆13Apr 15, 2025Updated last year
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- DCC is the first data-centric Machine Learning compiler for Processing-In-Memory (PIM) systems. More details in our ISCA 2026 paper by Ya…☆21Aug 3, 2026Updated 3 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆12Aug 29, 2020Updated 6 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 2 months ago
- ☆18Aug 10, 2026Updated 2 months ago
- GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…☆15Jun 24, 2020Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Mar 5, 2018Updated 8 years ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 2 months ago
- Ratatoskr NoC Simulator☆30Apr 13, 2021Updated 5 years ago
- ☆16Jul 16, 2026Updated 3 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An interconnection networks simulator☆14Jul 7, 2015Updated 11 years ago
- Netrace: a network packet trace reader☆16Jun 16, 2014Updated 12 years ago
- Convert Verilog to a Hardcaml design☆23Updated this week
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated last year
- ☆28Nov 15, 2019Updated 6 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆25Oct 31, 2024Updated 2 years ago
- systemc建模相关☆28Jun 11, 2014Updated 12 years ago
- Notes of basic subjects that fall under Electronics and Communication Engineering.☆16Jan 27, 2022Updated 4 years ago
- BloodCell-Detector-Yolo is a YOLOv5 implementation tailored to detect Red Blood Cells (RBC), White Blood Cells (WBC), and Platelets from …☆20Jan 23, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- EE577b-Course-Project☆19May 6, 2020Updated 6 years ago
- Gem5 with PCI Express integrated.☆26Sep 29, 2018Updated 8 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- RISC-V assembler/simulator with GUI☆14Jul 31, 2022Updated 4 years ago
- Algorithm to hardware compilation tools (e.g. C to VHDL).☆46Oct 13, 2026Updated 3 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆179Mar 12, 2026Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆72Feb 13, 2025Updated last year