zhipengzhaocmu / HLS_NoC
HLS code for Network on Chip (NoC)
☆11Updated 4 years ago
Related projects: ⓘ
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆13Updated 10 years ago
- ☆23Updated 4 years ago
- verification of simple axi-based cache☆16Updated 5 years ago
- ☆31Updated 2 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆11Updated 5 years ago
- Direct Access Memory for MPSoC☆12Updated this week
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- Design and UVM-TB of RISC -V Microprocessor☆12Updated 2 months ago
- ☆21Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆26Updated last year
- NoC based MPSoC☆10Updated 10 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆16Updated 5 years ago
- Network on Chip for MPSoC☆24Updated this week
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Implementation of the PCIe physical layer☆28Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆10Updated 8 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- The memory model was leveraged from micron.☆18Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Development of a Network on Chip Simulation using SystemC.☆30Updated 7 years ago
- ☆63Updated 9 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆27Updated 5 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- AHB Bus lite v3.0☆14Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆29Updated last year
- ☆16Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆19Updated 6 years ago