Alternatives and similar repositories for multihead_attn_accelerator

Users that are interested in multihead_attn_accelerator are comparing it to the libraries listed below

• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆18Updated last year
• ECASLab / hls-fpga-accelerators
  Collection of kernel accelerators optimised for LLM execution
  ☆22Updated 5 months ago
• booniebears / CoMN
  ☆18Updated last year
• bonanyan / attentionlego
  Attentionlego
  ☆12Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆29Updated last year
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆51Updated last year
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆88Updated 3 years ago
• gl9544 / vit_transformer_fpga
  ☆14Updated 2 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆63Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆87Updated 8 months ago
• gem5-X / TiC-SAT
  ☆17Updated 4 months ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated last year
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆11Updated 4 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆33Updated this week
• lsq314 / SpMM_TCAD
  ☆17Updated last year
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆51Updated 4 years ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆14Updated last month
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆63Updated 6 months ago
• RW999creator / GPP-PIM
  ☆11Updated 11 months ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆18Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• 19801201 / Ultra_low_power_CNN_Accelerated
  ☆10Updated 3 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆132Updated 4 months ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆12Updated 4 years ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆73Updated 6 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆116Updated 5 years ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆82Updated 3 months ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago