GT-CHIPS / gem5_chips
gem5 repository to study chiplet-based systems
☆72Updated 6 years ago
Alternatives and similar repositories for gem5_chips:
Users that are interested in gem5_chips are comparing it to the libraries listed below
- ☆30Updated 11 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 10 months ago
- A list of our chiplet simulaters☆32Updated last month
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆91Updated last year
- ☆29Updated 4 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆53Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- An Open-Source Tool for CGRA Accelerators☆64Updated 2 weeks ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆11Updated 2 weeks ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆126Updated last week
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆36Updated 2 years ago
- gem5 Tips & Tricks☆68Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- An integrated CGRA design framework☆88Updated last month
- ☆25Updated last year
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆109Updated 2 years ago