GT-CHIPS / gem5_chipsLinks
gem5 repository to study chiplet-based systems
☆74Updated 6 years ago
Alternatives and similar repositories for gem5_chips
Users that are interested in gem5_chips are comparing it to the libraries listed below
Sorting:
- ☆30Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆67Updated 11 months ago
- A list of our chiplet simulaters☆32Updated 2 months ago
- ☆32Updated 5 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- An integrated CGRA design framework☆88Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆12Updated last month
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆91Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- Benchmarks for Accelerator Design and Customized Architectures☆122Updated 5 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated 2 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆55Updated 5 months ago
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- ☆52Updated 2 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- ☆26Updated last year