GT-CHIPS / gem5_chipsLinks
gem5 repository to study chiplet-based systems
☆84Updated 6 years ago
Alternatives and similar repositories for gem5_chips
Users that are interested in gem5_chips are comparing it to the libraries listed below
Sorting:
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- ☆37Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆79Updated 6 years ago
- ☆105Updated last year
- ☆48Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An integrated CGRA design framework☆91Updated 7 months ago
- A list of our chiplet simulaters☆43Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆201Updated 5 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- Fast and accurate DRAM power and energy estimation tool☆185Updated last month
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆251Updated 3 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆64Updated 3 months ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆124Updated 7 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Updated 5 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 4 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆24Updated 4 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago