GT-CHIPS / gem5_chips
gem5 repository to study chiplet-based systems
☆72Updated 5 years ago
Alternatives and similar repositories for gem5_chips:
Users that are interested in gem5_chips are comparing it to the libraries listed below
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆63Updated 9 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆61Updated 3 months ago
- ☆28Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- ☆91Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆51Updated 4 months ago
- ☆29Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- A list of our chiplet simulaters☆32Updated last week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆51Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆122Updated last week
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- ☆48Updated 2 weeks ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆65Updated last month
- ☆23Updated 4 years ago
- ☆26Updated 5 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- CGRA framework with vectorization support.☆29Updated this week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆108Updated 2 years ago