jgoeders / dac_sdc_2022
☆16Updated 2 years ago
Alternatives and similar repositories for dac_sdc_2022:
Users that are interested in dac_sdc_2022 are comparing it to the libraries listed below
- ☆21Updated 2 years ago
- ☆17Updated 2 years ago
- ☆39Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆20Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆11Updated 11 months ago
- Open-source of MSD framework☆16Updated last year
- ☆26Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆78Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- Verilog implementation of Softmax function☆60Updated 2 years ago
- ☆26Updated 3 months ago
- ☆44Updated 6 years ago
- DAC System Design Contest 2020☆29Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 6 months ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆38Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆91Updated 3 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆33Updated 6 years ago
- ☆19Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆14Updated last year