Alternatives and similar repositories for dac_sdc_2022

Users that are interested in dac_sdc_2022 are comparing it to the libraries listed below

• jgoeders / dac_sdc_2022_designs
  ☆17Updated 2 years ago
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 3 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 5 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated 2 years ago
• xliu0709 / DACSDC2021
  ☆11Updated last year
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆41Updated 9 months ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆83Updated 3 years ago
• yportne13 / SpinalResNet
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆33Updated 4 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆113Updated 4 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆52Updated 7 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 3 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 5 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆90Updated 6 years ago
• mfarhadi / CNNIOT
  ☆46Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆23Updated last year
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆64Updated 5 months ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆45Updated 4 years ago