Alternatives and similar repositories for Risco-5

Users that are interested in Risco-5 are comparing it to the libraries listed below

• LSC-Unicamp / processor-ci-website
  Processor CI project Website
  ☆10Updated 3 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆117Updated last week
• riscv-software-src / riscv-ctg
  ☆41Updated 11 months ago
• racerxdl / riskow
  Learning how to make a RISC-V
  ☆135Updated 4 years ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆183Updated 6 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆184Updated 2 weeks ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆113Updated 4 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆301Updated 7 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆287Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 4 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆111Updated this week
• riscv-software-src / riscof
  ☆92Updated last month
• chipsalliance / VeeR-ISS
  ☆145Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated this week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆38Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated 3 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆136Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 3 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 10 months ago
• bsc-loca / sargantana
  ☆108Updated last month