pietroglyph / pipelined-rv32iLinks
A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)
☆10Updated last year
Alternatives and similar repositories for pipelined-rv32i
Users that are interested in pipelined-rv32i are comparing it to the libraries listed below
Sorting:
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆167Updated last week
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆50Updated last year
- Verilog implementation of multi-stage 32-bit RISC-V processor☆115Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated last week
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆72Updated last month
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆90Updated 4 months ago
- A simple RISC V core for teaching☆192Updated 3 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆203Updated 2 weeks ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆107Updated last year
- Verilog UART☆173Updated 12 years ago
- RISC-V RV32I CPU core☆25Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆142Updated 3 years ago
- RISC-V microcontroller IP core developed in Verilog☆174Updated 3 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- 32 bit RISC-V CPU implementation in Verilog☆31Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Basic RISC-V Test SoC☆137Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆62Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- This repository contains the design files of RISC-V Single Cycle Core☆51Updated last year
- Verification IP for I2C protocol☆46Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆215Updated this week
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆83Updated 2 years ago
- Implementation of RISC-V RV32I☆19Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago