Adham-Mohamed-Ahmed-Abd-Elrahim / Pipelined_MIPS_32-bit_harvard-arch
☆13Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for Pipelined_MIPS_32-bit_harvard-arch
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆108Updated this week
- Synthesizable temperature sensor for Tiny Tapeout 03, developed by IIC@JKU.☆20Updated 10 months ago
- ☆78Updated last year
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- ☆57Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- A tube guitar amplifier power supply VHDL project☆16Updated last week
- An open-source HDL register code generator fast enough to run in real time.☆36Updated this week
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆46Updated 2 weeks ago
- ☆52Updated last year
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆14Updated 3 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆94Updated last year
- ☆22Updated last week
- ☆31Updated last week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- ☆40Updated 8 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- A set of rules and recommendations for analog and digital circuit designers.☆25Updated 2 weeks ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆14Updated 3 weeks ago
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆20Updated 3 years ago
- ☆13Updated last month
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 3 weeks ago
- ☆69Updated 2 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- A compact, configurable RISC-V core☆11Updated last week
- ☆19Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆45Updated last month