wyvernSemi / riscV

Related projects ⓘ

Alternatives and complementary repositories for riscV

• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆75Updated last year
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual host model for verilog
  ☆84Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 6 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• chipsalliance / Cores-SweRV_fpga
  ☆39Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆29Updated 5 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆56Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆57Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago