Alternatives and similar repositories for ahb3lite_pkg

Users that are interested in ahb3lite_pkg are comparing it to the libraries listed below

• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆21Updated 10 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• PeterMonsson / sv_waveterm
  ☆10Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated this week
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 8 months ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 5 months ago
• pulp-platform / axi_llc
  ☆29Updated last month
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆29Updated 6 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆43Updated last year
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 5 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 weeks ago
• merldsu / PY_UVM_Framework
  This repo contain the PY-UVM Framework for different RISC-V Cores
  ☆31Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆12Updated 3 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• rgwan / AMBA
  Collection of IPs based on AMBA (AHB, APB, AXI) protocols
  ☆19Updated 8 years ago