intel / rohd-hclLinks
A hardware component library developed with ROHD.
☆111Updated this week
Alternatives and similar repositories for rohd-hcl
Users that are interested in rohd-hcl are comparing it to the libraries listed below
Sorting:
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆46Updated 4 months ago
- ☆114Updated 3 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆111Updated last week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- Control and status register code generator toolchain☆172Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated 3 weeks ago
- RISC-V Verification Interface☆138Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆70Updated this week
- An overview of TL-Verilog resources and projects☆82Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- SystemVerilog frontend for Yosys☆196Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆137Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆239Updated this week
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆119Updated 4 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- RISC-V System on Chip Template☆160Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Curriculum for a university course to teach chip design using open source EDA tools☆133Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago
- A demo system for Ibex including debug support and some peripherals☆84Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆267Updated last week
- Announcements related to Verilator☆43Updated 3 months ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆201Updated this week