arhamhashmi01 / rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
☆10Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for rv32i-pipeline-processor
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- ☆10Updated 4 months ago
- ☆19Updated this week
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆12Updated last year
- ☆39Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- ☆16Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆15Updated 8 months ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- ☆26Updated 7 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Complete tutorial code.☆12Updated 6 months ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- To design test bench of the APB protocol☆15Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- The memory model was leveraged from micron.☆19Updated 6 years ago
- ☆22Updated 8 months ago