My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris and David Harris
☆46Jun 2, 2023Updated 3 years ago
Alternatives and similar repositories for RISCV_Single_Cycle_Processor
Users that are interested in RISCV_Single_Cycle_Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains the design files of RISC-V Single Cycle Core☆85Dec 14, 2023Updated 2 years ago
- RISC-V processor model☆11Nov 10, 2020Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆149Oct 2, 2025Updated 9 months ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- Projects corresponding to the domain of electronic and vision-based bio-medical engineering.☆12Sep 11, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- Verilog modules for beginners☆29May 27, 2022Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆32Feb 21, 2019Updated 7 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆27Jun 4, 2024Updated 2 years ago
- I am developing a set of general-purpose shareable data structures for C# and Java all of whose fields are public readonly/final, and use…☆11Jun 22, 2026Updated 2 weeks ago
- Compressed Sensing signal decoding with DNN oracle on STM32☆16Apr 5, 2021Updated 5 years ago
- ☆12Jul 7, 2020Updated 6 years ago
- Machine learning algorithms applied into real modern robot, also the base package for visual SLAM project.☆11Oct 20, 2018Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆60Jan 28, 2025Updated last year
- Projects, Codes, Notes, Fixes and Results for book "Hands-On RTOS with Microcontrollers" by Brian Amos and published by Packt.☆12Mar 15, 2025Updated last year
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆38Oct 29, 2023Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆44Mar 2, 2022Updated 4 years ago
- Official PyTorch Code for "Dynamic Temperature Knowledge Distillation"☆11Mar 28, 2025Updated last year
- My 32-bit RISC CPU for smallish FPGAs☆19Apr 20, 2022Updated 4 years ago
- Design of miller compensated 2 stage opamp using open source SKY130PDK☆15Jun 18, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- + It's a simple project where you'll learn how to create a Robotic Arm with Arduino board, controlled by a Android smartphone using Bl…☆33Mar 4, 2018Updated 8 years ago
- Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA☆12Mar 29, 2018Updated 8 years ago
- A 30 day Web Development bootcamp organised by TinkerHubs of UCEK, CET, LBSITW, CEC, GCEB and TKMCE☆17May 26, 2023Updated 3 years ago
- 32-bit RISC processor☆23Jan 7, 2019Updated 7 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆30Apr 29, 2024Updated 2 years ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆14May 16, 2024Updated 2 years ago
- ☆15Aug 3, 2021Updated 4 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated 2 years ago
- 使用verilog实现流水线 FFT☆16Jul 1, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆45Mar 22, 2019Updated 7 years ago
- A Single Cycle Risc-V 32 bit CPU☆73Jan 14, 2026Updated 5 months ago
- AI Accelerators-SC23-tutorial Repository☆12Nov 12, 2023Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Arduino firmware for various development boards to use with chords.upsidedownlabs.tech☆28May 15, 2026Updated last month