Single Cycle CPU using the RV32I Base Instruction set
☆25Nov 5, 2025Updated 11 months ago
Alternatives and similar repositories for Single-Cycle-RV32I
Users that are interested in Single-Cycle-RV32I are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Single Cycle Risc-V 32 bit CPU☆78Jan 14, 2026Updated 9 months ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆47Dec 5, 2019Updated 6 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆45Oct 29, 2023Updated 3 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆43Mar 25, 2020Updated 6 years ago
- Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA☆32Apr 23, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Single-Cycle RISC-V Processor in systemverylog☆28Apr 23, 2019Updated 7 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆90Dec 14, 2023Updated 2 years ago
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆33Nov 18, 2025Updated 11 months ago
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆12Dec 31, 2024Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆78May 8, 2021Updated 5 years ago
- Probably the easist way to manage and visualize your Openhaystack devices☆10Aug 19, 2025Updated last year
- A web-based graphical simulator of a simple 32-bit, single-cycle implementation of RISC-V☆30Mar 16, 2025Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Custom ECU (firmware and hardware) for Bespoke Electric Vehicles☆13Aug 13, 2026Updated 2 months ago
- Line coding and clock recovery for a fibre optic link, running on a Spartan 6 FPGA☆14May 29, 2017Updated 9 years ago
- A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication☆47Jul 13, 2026Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated 2 months ago
- This repository contains the design files of RISC-V Pipeline Core☆78May 11, 2023Updated 3 years ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆49Oct 12, 2026Updated 2 weeks ago
- Clock Data Recovery | 時鐘數據恢復☆12Aug 9, 2020Updated 6 years ago
- Simple runtime for Pulp platforms☆56Jul 7, 2026Updated 3 months ago
- The multi-core cluster of a PULP system.☆122Oct 5, 2026Updated 3 weeks ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Python code for Beaglebone Green Wireless - 3d Area Scanning☆17Mar 10, 2025Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆51Jun 19, 2024Updated 2 years ago
- Board definition files and initial example programs☆22Aug 7, 2021Updated 5 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆20Apr 17, 2021Updated 5 years ago
- Running Linux on IOb-SoC-OpenCryptoHW☆16Aug 15, 2024Updated 2 years ago
- ☆15Jul 27, 2018Updated 8 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆16Oct 10, 2020Updated 6 years ago
- Verilog implementation of a RISC-V core☆155Oct 11, 2018Updated 8 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- Structured UVM Course☆77Jan 4, 2024Updated 2 years ago
- This is a detailed SystemVerilog course☆172Mar 4, 2025Updated last year
- Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU☆14Jan 17, 2022Updated 4 years ago
- XLSynth: Accelerated HW Synthesis☆18Updated this week
- ☆15Nov 12, 2020Updated 5 years ago
- ☆16Oct 5, 2026Updated 3 weeks ago