PebPeb / Single-Cycle-RV32ILinks
Single Cycle CPU using the RV32I Base Instruction set
☆18Updated 3 months ago
Alternatives and similar repositories for Single-Cycle-RV32I
Users that are interested in Single-Cycle-RV32I are comparing it to the libraries listed below
Sorting:
- 32 bit RISC-V CPU implementation in Verilog☆34Updated 3 years ago
- fpga verilog risc-v rv32i cpu☆14Updated 2 years ago
- Simple RiscV core for academic purpose.☆23Updated 5 years ago
- Simple 8-bit UART realization on Verilog HDL.☆114Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆145Updated 6 years ago
- UART implementation using verilog☆31Updated 2 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆56Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- 32-bit soft RISCV processor for FPGA applications☆19Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆76Updated 2 years ago
- ☆34Updated last month
- A simple implementation of a UART modem in Verilog.☆171Updated 4 years ago
- Verilog UART☆192Updated 12 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆91Updated last year
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated this week
- Labs to learn SpinalHDL☆153Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.☆45Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆39Updated 6 years ago
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- Quite OK Image FPGA Encoder and Decoder☆24Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆200Updated this week
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆29Updated 2 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆201Updated this week