uwsampl / lastlayerLinks
Towards Hardware and Software Continuous Integration
☆13Updated 5 years ago
Alternatives and similar repositories for lastlayer
Users that are interested in lastlayer are comparing it to the libraries listed below
Sorting:
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 2 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- A Hardware Pipeline Description Language☆49Updated 6 months ago
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- ☆24Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- ☆30Updated 6 years ago
- ☆104Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Updated 7 months ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- ☆82Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Updated last year
- ☆88Updated 3 years ago
- ☆14Updated 3 years ago
- Next generation CGRA generator☆118Updated this week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 3 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago