datenlord / blue-rdma
RoCEv2 hardware implementation in Bluespec SystemVerilog
☆23Updated 6 months ago
Alternatives and similar repositories for blue-rdma:
Users that are interested in blue-rdma are comparing it to the libraries listed below
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Ethernet switch implementation written in Verilog☆44Updated last year
- BlackParrot on Zynq☆35Updated 3 weeks ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- corundum work on vu13p☆18Updated last year
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆26Updated 8 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆26Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆21Updated 2 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Distributed Accelerator OS☆63Updated 2 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆22Updated last year
- ☆25Updated last year
- ☆16Updated 3 years ago
- ☆53Updated 4 years ago
- ☆24Updated last month
- TCAM (Ternary Content-Addressable Memory) in Verilog☆46Updated last year
- ☆23Updated 3 years ago
- ☆14Updated last month
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆46Updated 4 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆42Updated last year
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆43Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- ☆14Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago