Alternatives and similar repositories for gem5_Garnet2.0_extensions

Users that are interested in gem5_Garnet2.0_extensions are comparing it to the libraries listed below

• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆56Updated 8 years ago
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆39Updated 3 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆74Updated 6 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆31Updated 3 weeks ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 5 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆82Updated 11 years ago
• bheemhh1 / 3D_NoC
  Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures
  ☆12Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆70Updated last month
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆47Updated 7 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆25Updated 10 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆82Updated 4 months ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆86Updated 5 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆27Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆72Updated 6 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆45Updated 2 years ago
• ceunican / tpzsimul
  Automatically exported from code.google.com/p/tpzsimul
  ☆14Updated 10 years ago
• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year