FAST-9 Accelerator for Corner Detection
☆38Jan 1, 2021Updated 5 years ago
Alternatives and similar repositories for FAST9-Accelerator
Users that are interested in FAST9-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design real-time image processing, object recognition and PID control for Autonomous Drone.☆35Nov 26, 2017Updated 8 years ago
- FPGA FAST image feature detector implementation in VHDL☆38Nov 14, 2022Updated 3 years ago
- C source code for FAST corner detectors☆102Apr 18, 2018Updated 7 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆14May 3, 2012Updated 13 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- ☆30Aug 19, 2019Updated 6 years ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 2 months ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 3 weeks ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆74Sep 3, 2019Updated 6 years ago
- ☆15Nov 16, 2020Updated 5 years ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- Virtual Platform for AWS FPGA support☆16Oct 19, 2018Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- Cryptonight Monero Verilog code for ASIC☆20Mar 29, 2018Updated 7 years ago
- ☆35Mar 8, 2023Updated 3 years ago
- ☆13Jul 28, 2022Updated 3 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆31Nov 3, 2025Updated 4 months ago
- ☆21Apr 8, 2025Updated 11 months ago
- ☆36Jun 19, 2023Updated 2 years ago
- ☆23Mar 15, 2025Updated last year
- Examples from the book by Deschamps et al. https://www.amazon.com/Implementation-Arithmetic-Functions-Electrical-Engineering/dp/940072986…☆18Apr 17, 2019Updated 6 years ago
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Programmatically control ROS Bag files.☆13Sep 5, 2017Updated 8 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆41Mar 1, 2019Updated 7 years ago
- LLVM 2.9 branch with TI C64x backend.☆11Oct 17, 2019Updated 6 years ago
- Convert AEDAT4 files from DV into AEDAT-2.0 files for jAER☆10Feb 23, 2024Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Course content for the University of Bristol Design Verification course.☆64Oct 1, 2025Updated 5 months ago
- A library to parse BLIF (Berkeley Logic Interchange Format) files.☆10Mar 11, 2015Updated 11 years ago
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last month
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- Toolchain for FPGA-based smart camera by Dream Team IP☆16Oct 8, 2018Updated 7 years ago