kwonalbert / oram_fpgaLinks
FPGA related files for ORAM
☆14Updated 9 years ago
Alternatives and similar repositories for oram_fpga
Users that are interested in oram_fpga are comparing it to the libraries listed below
Sorting:
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- ☆81Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 6 months ago
- DASS HLS Compiler☆29Updated last year
- ☆18Updated last year
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆32Updated last year
- ☆15Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ILA Model Database☆23Updated 4 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ☆13Updated 10 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- A Hardware Pipeline Description Language☆45Updated last month
- CGRA framework with vectorization support.☆34Updated this week
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆18Updated 8 months ago
- ☆58Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆27Updated 7 years ago
- ☆15Updated 4 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- ☆33Updated 4 months ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago