kwonalbert / oram_fpgaLinks
FPGA related files for ORAM
☆14Updated 10 years ago
Alternatives and similar repositories for oram_fpga
Users that are interested in oram_fpga are comparing it to the libraries listed below
Sorting:
- ☆20Updated last year
- ☆17Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆28Updated 2 years ago
- CGRA framework with vectorization support.☆42Updated last week
- ☆82Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 11 months ago
- ILA Model Database☆24Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- ☆19Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆29Updated 8 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- The OpenPiton Platform☆28Updated 2 years ago
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆19Updated 9 years ago
- ☆60Updated 2 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆13Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆140Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆27Updated 7 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago