TonyBrewer / OpenHTLinks
Hybrid Threading Tool Set
☆15Updated 5 years ago
Alternatives and similar repositories for OpenHT
Users that are interested in OpenHT are comparing it to the libraries listed below
Sorting:
- ☆24Updated 4 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆44Updated 8 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆54Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- ☆60Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 11 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Algorithmic C Machine Learning Library☆26Updated 2 weeks ago
- Spector: An OpenCL FPGA Benchmark Suite☆48Updated 6 years ago
- ☆87Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago