akashlevy / pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
☆13Updated 5 years ago
Alternatives and similar repositories for pyxbar
Users that are interested in pyxbar are comparing it to the libraries listed below
Sorting:
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆65Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- sram/rram/mram.. compiler☆34Updated last year
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆59Updated 2 weeks ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Architecture for RRAM multilevel programming☆17Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆23Updated 5 months ago
- Physical memristor/RRAM/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices sett…☆44Updated 5 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆35Updated 3 weeks ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆14Updated 8 months ago
- CNN accelerator☆27Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 3 months ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆15Updated 4 years ago