ARM-software / DeepFreezeLinks
☆40Updated 5 years ago
Alternatives and similar repositories for DeepFreeze
Users that are interested in DeepFreeze are comparing it to the libraries listed below
Sorting:
- Tutorials on HLS Design☆52Updated 5 years ago
- ☆85Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- Train and deploy LUT-based neural networks on FPGAs☆99Updated last year
- ☆60Updated 5 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆72Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- A DSL for Systolic Arrays☆81Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆23Updated 6 years ago
- ☆35Updated 6 years ago
- ☆71Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- MAERI public release☆31Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- ☆30Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆89Updated last week
- Public release☆56Updated 6 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆28Updated 7 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 3 months ago