monotone-RK / FACELinks
FACE: Fast and Customizable Sorting Accelerator
☆11Updated 9 years ago
Alternatives and similar repositories for FACE
Users that are interested in FACE are comparing it to the libraries listed below
Sorting:
- Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code☆17Updated 9 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 8 years ago
- CNN accelerator☆27Updated 8 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Updated 5 years ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- ☆15Updated 3 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 9 years ago
- PCI Express controller model☆69Updated 3 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆83Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 8 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆24Updated 3 weeks ago
- ☆14Updated 9 years ago
- ☆15Updated 4 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- SmartNIC☆14Updated 6 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 11 years ago