UCSBarchlab / Charm
A Language for Closed-form High-level ARchitecture Modeling
☆20Updated 5 years ago
Alternatives and similar repositories for Charm:
Users that are interested in Charm are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- CGRA framework with vectorization support.☆25Updated this week
- A polyhedral compiler for hardware accelerators☆55Updated 6 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- ☆54Updated this week
- ☆23Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- Floating point modules for CHISEL☆31Updated 10 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- HeteroCL-MLIR dialect for accelerator design☆41Updated 5 months ago
- ☆15Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆57Updated 4 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆61Updated 3 years ago
- ILA Model Database☆22Updated 4 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆15Updated 3 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- EQueue Dialect☆40Updated 3 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆61Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year