Alternatives and similar repositories for Charm

Users that are interested in Charm are comparing it to the libraries listed below

• sfu-arch / muir
  ☆24Updated 5 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆52Updated 6 years ago
• StanfordAHA / aha
  ☆62Updated 3 weeks ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆43Updated 6 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆48Updated 3 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆25Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆35Updated 2 years ago
• icgrp / hipr
  ☆17Updated 2 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆24Updated 4 years ago
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆67Updated 8 years ago
• lana555 / dynamatic
  ☆87Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆70Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated last week
• StanfordAHA / Halide-to-Hardware_archive
  ☆82Updated 11 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆169Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆90Updated 2 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆23Updated this week