nvdla / simple_cpuLinks
NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)
☆22Updated 7 years ago
Alternatives and similar repositories for simple_cpu
Users that are interested in simple_cpu are comparing it to the libraries listed below
Sorting:
- Virtual Platform for NVDLA☆161Updated 7 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆36Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- Next generation CGRA generator☆118Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)☆30Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- SystemC training aimed at TLM.☆35Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Public release☆58Updated 6 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- ☆87Updated last week
- The multi-core cluster of a PULP system.☆111Updated this week
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Updated 7 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- An open-source UCIe implementation☆82Updated last week
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Updated last year
- OpenDesign Flow Database☆17Updated 7 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- PACoGen: Posit Arithmetic Core Generator☆76Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Updated 6 years ago