Alternatives and similar repositories for slang-server

Users that are interested in slang-server are comparing it to the libraries listed below

• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• antmicro / sv-bugpoint
  ☆30Updated last week
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆97Updated 2 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 10 months ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated 3 weeks ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆42Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 6 months ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• projectapheleia / avl
  Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb
  ☆40Updated 3 weeks ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• TsaiAnson / verif
  ☆12Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆51Updated 3 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated this week
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆67Updated 11 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 2 weeks ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆18Updated 3 weeks ago
• pulp-platform / cheshire-ihp130-o
  ☆57Updated 7 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆14Updated 9 years ago