Alternatives and similar repositories for oombak

Users that are interested in oombak are comparing it to the libraries listed below

• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• pieter3d / simview
  ☆79Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆53Updated 2 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated last week
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 3 years ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆53Updated 3 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆67Updated 2 weeks ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆16Updated last week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆46Updated 3 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆46Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated 2 weeks ago
• ldoolitt / vhd2vl
  ☆135Updated 8 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆117Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 10 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆53Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆153Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆91Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year