Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
☆51Apr 11, 2026Updated 2 months ago
Alternatives and similar repositories for oombak
Users that are interested in oombak are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 10 months ago
- A web-based RISC-V simulator https://riscv-simulator-five.vercel.app☆64May 1, 2026Updated 2 months ago
- A Rust to Ada/SPARK converter that makes your systems immune to the Rust virus. Converts Rust code to formally verifiable Ada, including …☆22Apr 22, 2025Updated last year
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 11 months ago
- Clarvi simple RISC-V processor for teaching☆58Aug 25, 2017Updated 8 years ago
- rust ftdi ft60x libusb driver☆16Dec 16, 2020Updated 5 years ago
- Hardware transactions library for Amaranth☆27Updated this week
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 8 months ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆31Jun 26, 2026Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Updated this week
- Implementation of webassembly code based on nodejs napi-addon.☆11Mar 11, 2019Updated 7 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆31Apr 9, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- MIPI DSI controller☆86Jun 27, 2022Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- A tool for synthesizing Verilog programs☆116Aug 25, 2025Updated 10 months ago
- ☆11Nov 17, 2025Updated 7 months ago
- SNES for MiSTer☆16Sep 5, 2025Updated 10 months ago
- bil verification tool☆12Jun 30, 2022Updated 4 years ago
- A repository of information and source files for toolflow-supported hardware☆36Jul 15, 2022Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- A Docker image for Mentor/Siemens Questa☆13Sep 26, 2023Updated 2 years ago
- A modern schematic entry and simulation program☆94Updated this week
- fbDOOM with RISC-V Vector optimizations☆17Aug 30, 2023Updated 2 years ago
- This repo hold information on the open-standard OVP APIs☆20Dec 11, 2025Updated 6 months ago
- ☆49Jan 23, 2026Updated 5 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆315Updated this week
- CAN 2.0B Controller in VHDL and Verilog☆11Nov 22, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 9 months ago
- C++ Parser for the Carto stylesheet language☆15Oct 10, 2014Updated 11 years ago
- A YM2413 clone module written in VHDL.☆30Aug 18, 2020Updated 5 years ago
- Scalable Interface for RISC-V ISA Extensions☆26Jun 9, 2026Updated 3 weeks ago
- Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı☆15May 27, 2023Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago