Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
☆51Apr 11, 2026Updated 3 weeks ago
Alternatives and similar repositories for oombak
Users that are interested in oombak are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 8 months ago
- A web-based RISC-V simulator https://riscv-simulator-five.vercel.app☆56Updated this week
- A Rust to Ada/SPARK converter that makes your systems immune to the Rust virus. Converts Rust code to formally verifiable Ada, including …☆21Apr 22, 2025Updated last year
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Repository for Hornet RISC-V Core☆20Sep 15, 2022Updated 3 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 9 months ago
- Clarvi simple RISC-V processor for teaching☆58Aug 25, 2017Updated 8 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 6 months ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆31Nov 28, 2025Updated 5 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆96Apr 10, 2026Updated 3 weeks ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆31Apr 9, 2026Updated 3 weeks ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Mar 27, 2026Updated last month
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- A tool for synthesizing Verilog programs☆114Aug 25, 2025Updated 8 months ago
- ☆11Nov 17, 2025Updated 5 months ago
- SNES for MiSTer☆16Sep 5, 2025Updated 8 months ago
- bil verification tool☆12Jun 30, 2022Updated 3 years ago
- A repository of information and source files for toolflow-supported hardware☆35Jul 15, 2022Updated 3 years ago
- SystemVerilog Linter based on pyslang☆32May 5, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Docker image for Mentor/Siemens Questa☆13Sep 26, 2023Updated 2 years ago
- A modern schematic entry and simulation program☆93Apr 24, 2026Updated last week
- fbDOOM with RISC-V Vector optimizations☆17Aug 30, 2023Updated 2 years ago
- This repo hold information on the open-standard OVP APIs☆20Dec 11, 2025Updated 4 months ago
- ☆49Jan 23, 2026Updated 3 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆288Apr 29, 2026Updated last week
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 3 months ago
- CAN 2.0B Controller in VHDL and Verilog☆11Nov 22, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 7 months ago
- Extract opening hours tags from a camera image☆11Apr 25, 2021Updated 5 years ago
- C++ Parser for the Carto stylesheet language☆15Oct 10, 2014Updated 11 years ago
- Scalable Interface for RISC-V ISA Extensions☆25Apr 7, 2026Updated 3 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆120Apr 1, 2024Updated 2 years ago
- Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı☆15May 27, 2023Updated 2 years ago
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago