fuad1502 / oombakLinks
Oombak π is an interactive SystemVerilog simulator UI that runs on your terminal!
β43Updated last month
Alternatives and similar repositories for oombak
Users that are interested in oombak are comparing it to the libraries listed below
Sorting:
- SystemVerilog Linter based on pyslangβ31Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttlesβ36Updated 2 years ago
- USB virtual model in C++ for Verilogβ31Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sourcesβ36Updated 3 weeks ago
- Python script to transform a VCD file to wavedrom formatβ80Updated 3 years ago
- SpiceBind β spice inside HDL simulatorβ54Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.β118Updated 2 years ago
- Making cocotb testbenches that bit easierβ36Updated 2 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulatorβ75Updated 2 months ago
- Flip flop setup, hold & metastability explorer toolβ50Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.β21Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb exampleβ18Updated 9 months ago
- UART cocotb moduleβ11Updated 4 years ago
- Greyhound on IHP SG13G2 0.13 ΞΌm BiCMOS processβ56Updated 2 weeks ago
- LunaPnR is a place and router for integrated circuitsβ47Updated 2 months ago
- Virtual development board for HDL designβ42Updated 2 years ago
- β80Updated last week
- Specification of the Wishbone SoC Interconnect Architectureβ45Updated 3 years ago
- RISC-V Nox coreβ68Updated 2 months ago
- Trying to verify Verilog/VHDL designs with formal methods and toolsβ42Updated last year
- An open-source HDL register code generator fast enough to run in real time.β73Updated last week
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensourβ¦β16Updated 2 weeks ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)β66Updated 7 months ago
- β34Updated 4 years ago
- π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.β29Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAsβ74Updated 2 years ago
- β32Updated 8 months ago
- SystemVerilog FSM generatorβ32Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the β¦β54Updated this week
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debβ¦β24Updated 3 weeks ago