High quality and composable RTL libraries in SystemVerilog
☆44Jul 24, 2026Updated this week
Alternatives and similar repositories for bedrock-rtl
Users that are interested in bedrock-rtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆36May 21, 2026Updated 2 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- ☆21Updated this week
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆47Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆21Jun 14, 2026Updated last month
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- ☆46Jul 17, 2026Updated last week
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Jul 2, 2026Updated 3 weeks ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- RTL data structure☆69Apr 23, 2026Updated 3 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆52Jan 13, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆17Dec 14, 2025Updated 7 months ago
- Bazel build rules for compiling Verilog☆22Mar 4, 2024Updated 2 years ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Updated this week
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated 2 weeks ago
- ☆21May 8, 2025Updated last year
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆27Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Control and status register code generator toolchain☆201Jul 14, 2026Updated last week
- Vmodel toolbox repository☆15Mar 25, 2016Updated 10 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- A modular hardware abstraction library☆55Updated this week
- a naive static http server that solves C10K problem☆17Jan 8, 2017Updated 9 years ago
- HW Design Collateral for Caliptra RoT IP☆148Updated this week
- ☆40Sep 17, 2021Updated 4 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Mar 3, 2026Updated 4 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Basic Simulink Blocks for modeling CDRs and PLLs☆16Apr 25, 2020Updated 6 years ago
- SystemVerilog FSM generator☆39May 10, 2026Updated 2 months ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆44Jan 15, 2024Updated 2 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- A SystemVerilog language server based on the Slang library.☆280Updated this week
- A fork of Yosys that integrates the CellIFT pass☆14Apr 21, 2026Updated 3 months ago
- ☆18Aug 26, 2016Updated 9 years ago