xlsynth / bedrock-rtlLinks
High quality and composable RTL libraries in SystemVerilog
☆27Updated this week
Alternatives and similar repositories for bedrock-rtl
Users that are interested in bedrock-rtl are comparing it to the libraries listed below
Sorting:
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Hardware generator debugger☆76Updated last year
- A SystemVerilog source file pickler.☆60Updated 11 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆53Updated 4 months ago
- ☆16Updated 4 months ago
- A configurable SRAM generator☆56Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 weeks ago
- Python wrapper for verilator model☆89Updated last year
- Mutation Cover with Yosys (MCY)☆87Updated this week
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- A SystemVerilog language server based on the Slang parser and library.☆40Updated last week
- Advanced Debug Interface☆14Updated 8 months ago
- Equivalence checking with Yosys☆47Updated this week
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- ☆12Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆35Updated last week
- SystemVerilog FSM generator